A) Field of the Invention
The present invention relates to a semiconductor device and its manufacture method, and more particularly to a semiconductor device having shallow trench isolation (STI) and its manufacture method.
B) Description of the Related Art
Local oxidation of silicon (LOCOS) has been used as isolation of a semiconductor device.
According to LOCOS techniques, after a silicon oxide film is formed on a silicon substrate as a buffer layer, a silicon nitride film is formed as a mask layer for preventing oxidization. After the silicon nitride film is patterned, the surface of the silicon substrate is selectively and thermally oxidized via the silicon oxide film.
Oxidizing species such as oxygen and moisture enter not only a silicon region under an opening of the silicon nitride film (isolation region) but also a silicon region under the buffer silicon oxide layer under the nitride layer (active region) adjacent to the opening, when the silicon substrate is thermally oxidized.
These oxidizing species oxidize the silicon substrate surface even under the silicon nitride film and a silicon oxide region called birds' beak is formed. This bird's beak region cannot be substantially used as an active region for forming electronic elements so that the area of the active region is reduced.
A silicon nitride film having apertures of various sizes is formed on a silicon substrate and the substrate surface is thermally oxidized. In this case, a silicon oxide film formed on the silicon substrate surface and in the small size aperture is thinner than a silicon oxide film formed on the silicon substrate surface and in the large size aperture. This phenomenon is called thinning.
As a semiconductor device becomes miniaturized, a ratio of an area not used as the electronic element forming region to a total area of a semiconductor substrate increases. Namely, a ratio of the area unable to be used for the electronic element forming region, due to bird's beak or thinning, increases, hindering high integration of a semiconductor device.
Trench isolation (TI) techniques are known as isolation region forming techniques. According to TI techniques, a trench is formed in the surface layer of a semiconductor substrate and insulator or polysilicon is buried or embedded in the trench. This method has been used for forming a bipolar transistor LSI which requires deep isolation regions.
Trench isolation is being applied to a MOS transistor LSI because both bird's beak and thinning do not occur. MOS transistor LSI's do not require deep isolation regions like bipolar transistor LSI's and can use relatively shallow isolation regions having a depth of about 0.1 to 1.0 μm. This structure is called shallow trench isolation (STI).
STI forming processes will be described with reference to FIGS. 11A to 11G.
As shown in FIG. 11A, on the surface of a silicon substrate 1, a silicon oxide film 2 is formed having a thickness of, for example, 10 nm by thermal oxidation. On this silicon oxide film 2, a silicon nitride film 3 is formed having a thickness of, for example, 100 to 150 nm by chemical vapor deposition (CVD). The silicon oxide film 2 functions as a buffer layer for relaxing stress between the silicon substrate 1 and silicon nitride film 3. The silicon nitride film 3 functions as a stopper layer during a later polishing process.
On the silicon nitride film 3, a resist pattern 4 is formed. An opening defined by the resist pattern 4 defines an isolation region. The silicon substrate region under the resist pattern 4 defines the active region where electronic elements are to be formed.
By using the resist pattern 4 as an etching mask, the silicon nitride film 3, underlying silicon oxide film 2 and underlying silicon substrate 1 respectively exposed in the opening are etched by reactive etching (RIE) to a depth of, for example, about 0.5 μm to form a trench 6.
As shown in FIG. 11B, the silicon substrate surface exposed in the trench 6 is thermally oxidized to form a thermally oxidized silicon film 7 having a thickness of 10 nm for example.
As shown in FIG. 11C, a silicon oxide film 9 is deposited on the silicon substrate, for example, by high density plasma (HDP) CVD, the silicon oxide film 9 being buried or embedded in the trench. In order to make dense the silicon oxide film 9 which is used as the isolation region, the silicon substrate is annealed, for example, at 900 to 1100° C. in a nitrogen atmosphere.
As shown in FIG. 11D, the silicon oxide film 9 is polished downward by chemical mechanical polishing (CMP) or reactive ion etching (RIE) by using the silicon nitride film 3 as a stopper. The silicon oxide film 9 is therefore left only in the trench defined by the silicon nitride film 3. At this stage, annealing may be performed to make dense the silicon oxide film.
As shown in FIG. 11E, the silicon nitride film 3 is removed by using hot phosphoric acid. Next, the buffer silicon oxide film 2 on the surface of the silicon substrate 1 is removed by using dilute hydrofluoric acid. At this time, the silicon oxide film 9 buried in the trench is also etched to some degree.
As shown in FIG. 11F, the surface of the silicon substrate 1 is thermally oxidized to form a sacrificial silicon oxide film 22. Impurity ions of a desired conductivity type are implanted into the surface layer of the silicon substrate 1 via the sacrificial silicon oxide film, and activated to form a well 10 of the desired conductivity type in the surface layer of the silicon substrate 1. Thereafter, the sacrificial silicon oxide film 22 is removed by using dilute hydrofluoric acid. When the sacrificial silicon oxide film is removed, the silicon oxide film 9 is also etched to some degree by dilute hydrofluoric acid.
As shown in FIG. 11G, the exposed surface of the silicon substrate is thermally oxidized to form a silicon oxide film 11 having a desired thickness which is used as a gate insulating film. A polysilicon film 12 is deposited on the silicon substrate 1, and patterned to form a gate electrode. Impurity ions having an opposite conductivity type relative to that of the well 10 are implanted and activated to form source/drain regions. If necessary, side wall spacers are formed on the side walls of the gate electrode, and impurity ions of the opposite conductivity type are again implanted and activated to form high impurity concentration source/drain regions.
As the silicon oxide film 9 is buried in the trench and a heat treatment is performed for making it dense, the silicon oxide film 9 contracts as it becomes dense. The active region surrounded by the silicon oxide film 9 receives a compressive stress.
As the compressive stress is applied, the electron mobility in the active region of the silicon substrate may lower considerably. If the carrier mobility lowers, a saturated drain current reduces. As the active region becomes small as the semiconductor device is made miniaturized, the influence of compressive stress becomes large.
As the shoulder of the isolation region 9 is etched and a divot is formed as shown in FIG. 11G, not only the upper surface but also the side wall of the shoulder of the active region of the silicon substrate is surrounded by the gate electrode. As a voltage is applied to the gate electrode of such a shape, an electric field is concentrated upon the shoulder of the active region so that the shoulder forms a transistor having a lower threshold voltage. This parasitic transistor generates a hump on the IV characteristic curve.
A method of suppressing the formation of a divot and preventing the hump characteristics has been proposed (refer to Japanese Patent Laid-open Publication No. HEI-11-297812). According to this method, a silicon oxide film and a silicon nitride film are formed in this order on the inner surface of a trench, mask material is once filled in the trench, the mask material is then etched to such an extent that the surface level of the mask material in the trench becomes lower than the surface level of the semiconductor substrate, and the silicon nitride film exposed in the upper part of the trench above the mask material is removed.
A problem specific to STI may occur although STI is suitable for miniaturized fabrication. New techniques capable of overcoming the problem specific to STI has been desired.